Ambiente de programação descrito em VHDL para célula de memória analógica do tipo Floating-Gate

Fernando Cardoso Castaldo; Carlos Alberto dos Reis Filho

doi:10.5433/1679-0375.2005v26n1p51

VHDL-based programming environment for Floating-Gate analog memory cell

Authors

Fernando Cardoso Castaldo Universidade Estadual de Londrina
Carlos Alberto dos Reis Filho Universidade Estadual de Campinas

DOI:

https://doi.org/10.5433/1679-0375.2005v26n1p51

Keywords:

Floating-Gate, Trimming, VHDL.

Abstract

An implementation in CMOS technology of a Floating-Gate Analog Memory Cell and Programming Environment is presented. A digital closed-loop control compares a reference value set by user and the memory output and after cycling, the memory output is updated and the new value stored. The circuit can be used as analog trimming for VLSI applications where mechanical trimming associated with postprocessing chip is prohibitive due to high costs.

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Author Biographies

Fernando Cardoso Castaldo, Universidade Estadual de Londrina

Mestre e Doutor em Engenharia Elétrica na área de Sensores, Instrumentação Eletrônica e Microeletrônica. Atualmente Prof.Adjunto no Departamento de Eng. Elétrica da Universidade Estadual de Londrina.

Carlos Alberto dos Reis Filho, Universidade Estadual de Campinas

Mestre e Doutor em Engenharia Elétrica na área de Sensores, Instrumentação Eletrônica e Microeletrônica. Prof. Adjunto no Departamento de Instrumentação, Semicondutores e Fotônica da Faculdade de Engenharia Elétrica da Universidade Estadual de Campinas.

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Published

2005-07-15

How to Cite

Castaldo, F. C., & Reis Filho, C. A. dos. (2005). VHDL-based programming environment for Floating-Gate analog memory cell. Semina: Ciências Exatas E Tecnológicas, 26(1), 51–58. https://doi.org/10.5433/1679-0375.2005v26n1p51

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Issue

Vol. 26 No. 1 (2005)

Section

Original Article

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